On Fri, Apr 12, 2019 at 04:21:31PM +0200, Lars Persson wrote:
On 4/12/19 4:16 PM, Sasha Levin wrote:
On Fri, Apr 12, 2019 at 01:17:05PM +0200, Lars Persson wrote:
This was fixed in upstream by commit 7d9e6c5afab6 ("net: stmmac: Integrate
XGMAC into main driver flow") that is a new feature commit.
We found a race condition in the DMA init sequence that hits if the
PHY already has link up during stmmac_hw_setup. Since the ring length
was programmed after enabling the RX path, we might receive a packet
before the correct ring length is programmed. When that happened we
could not get reliable interrupts for DMA RX and the MTL complained
about RX FIFO overrun.
The correct init sequence according to the data book for DWC Ethernet
QoS 4.10 is:
1. Write Ring length
2. Write Descriptor list base address
3. Start the DMA.
Signed-off-by: Lars Persson <larper@xxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx # 4.9.x
Cc: Giuseppe Cavallaro <peppe.cavallaro@xxxxxx>
Cc: Alexandre Torgue <alexandre.torgue@xxxxxx>
Cc: Jose Abreu <joabreu@xxxxxxxxxxxx>
What about 4.14? 7d9e6c5afab6 isn't in it either.
I will send a separate patch for 4.14 in some days.
Okay. I can't merge this one until we have the 4.14 as well (otherwise,
people who upgrade from 4.9 to 4.14 will see a regression), so when it's
posted I can do both.
--
Thanks,
Sasha
