Quoting Weiyi Lu (2019-03-04 21:05:44) > In previous MediaTek PLL design, it assumes the pcw change control > is always on the CON1 register. > However, the pcw change bit on MT8183 was moved onto CON0 because > the the PCW length of audio PLLs are extended to 32-bit. > Add configurable pcw_chg_reg to set the pcw change control register > address or using the default control register CON1 if without > setting in pll data. > > Signed-off-by: Weiyi Lu <weiyi.lu@xxxxxxxxxxxx> > --- Applied to clk-next
