Patch "drm/i915: Fix pipe CSC post offset calculation" has been added to the 3.12-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/i915: Fix pipe CSC post offset calculation

to the 3.12-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-i915-fix-pipe-csc-post-offset-calculation.patch
and it can be found in the queue-3.12 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.


>From 32cf0cb0294814cb1ee5d8727e9aac0e9aa80d2e Mon Sep 17 00:00:00 2001
From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Date: Thu, 28 Nov 2013 22:10:38 +0200
Subject: drm/i915: Fix pipe CSC post offset calculation

From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>

commit 32cf0cb0294814cb1ee5d8727e9aac0e9aa80d2e upstream.

We were miscalculating the pipe CSC post offset for the full->limited
range conversion. The resulting post offset was double what it was
supposed to be, which caused blacks to come out grey when using
limited range output on HSW+.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71769
Tested-by: Lauri Mylläri <lauri.myllari@xxxxxxxxx>
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>

---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5546,7 +5546,7 @@ static void intel_set_pipe_csc(struct dr
 		uint16_t postoff = 0;
 
 		if (intel_crtc->config.limited_color_range)
-			postoff = (16 * (1 << 13) / 255) & 0x1fff;
+			postoff = (16 * (1 << 12) / 255) & 0x1fff;
 
 		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
 		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);


Patches currently in stable-queue which might be from ville.syrjala@xxxxxxxxxxxxxxx are

queue-3.12/drm-i915-fix-pipe-csc-post-offset-calculation.patch
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