On Thu, 24 Jan 2019 17:16:37 +0100
Emil Lenngren <emil.lenngren@xxxxxxxxx> wrote:
> Hi,
>
> Den tors 24 jan. 2019 kl 16:28 skrev Stefan Roese <sr@xxxxxxx>:
> >
> > On 24.01.19 15:20, Boris Brezillon wrote:
> > > Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
> > > the cache content to 0xFF (depends on vendor implementation), so we
> > > must fill the page cache entirely even if we only want to program the
> > > data portion of the page, otherwise we might corrupt the BBM or user
> > > data previously programmed in OOB area.
> > >
> > > Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
> > > Reported-by: Stefan Roese <sr@xxxxxxx>
> > > Cc: <stable@xxxxxxxxxxxxxxx>
> > > Signed-off-by: Boris Brezillon <bbrezillon@xxxxxxxxxx>
> >
> > Works fine (limited testing only yet), so:
> >
> > Tested-by: Stefan Roese <sr@xxxxxxx>
> > Reviewed-by: Stefan Roese <sr@xxxxxxx>
> >
> > Thanks,
> > Stefan
> >
>
> Can this quirk be made vendor specific?
We can make it vendor specific, as long as it's an opt-in thing. This
way, the default behavior is the safest one, and only when we know a
chip does reset the cache content on a PROGRAM LOAD time can we add this
flag.
> It seems a waste of SPI
> transfer cycles to write 0xff to the whole OOB area when we only want
> to program the data area if the chip doesn't need this quirk.
> For which logic is this needed anyway? According to the GigaDevice
> datasheet, if a Program Load is followed by Program Execute,
> "uninitialized" bytes will be set to 0xff, which is the flow that is
> used by spinand core.
Except you're not guaranteed that the controller can fill the page in a
single spi_mem_exec_op() call (because of FIFO size limitations), so
you might have one PROGRAM LOAD followed by several PROGRAM RANDOM LOAD.
I guess most manufacturers reset the cache content at PROGRAM LOAD
time, but GigaDevice does not.
>
> /Emil
