Hi guys, On 14/01/2019 16:12, Julien Thierry wrote: > On 14/01/2019 15:56, Catalin Marinas wrote: >> On Tue, Jan 08, 2019 at 02:07:19PM +0000, Julien Thierry wrote: >>> When using VHE, the host needs to clear HCR_EL2.TGE bit in order >>> to interract with guest TLBs, switching from EL2&0 translation regime >>> to EL1&0. >>> >>> However, some non-maskable asynchronous event could happen while TGE is >>> cleared like SDEI. Because of this address translation operations >>> relying on EL2&0 translation regime could fail (tlb invalidation, >>> userspace access, ...). >> >> Why would an NMI context need to access user space? (just curious what >> breaks exactly without this patch; otherwise it looks fine) > > If I remember correctly, the SDEI interrupt might perform cache > maintenance with EL2&0 translation regime, but James can probably give > more detail (or correct me if I'm wrong). Yup, spot on. The APEI driver has to map/unmap memory using the fixmap. If it interrupts a guest, the TLB maintenance would affect EL1&0 instead. > Otherwise, if we decide to use the pseudo NMI for profiling with perf, I > believe the perf interrupt can access user space (although I'm not > completely sure whether that might be to record profiling data in > buffers shared with user space or something else). It does a stack walk, I think its the PERF_SAMPLE_CALLCHAIN feature, and the code is: arch/arm64/kernel/perf_callchain.c::user_backtrace() Thanks, James
