Hi, Greg, this patche depend on another patch which I have forgotten
to add a Cc: stable line.
Commit d06f8a2f1befb5a3d0aa660ab1c05e9b74445 ("MIPS: Loongson-3: Fix
CPU UART irq delivery problem").
Huacai
On Sun, Nov 11, 2018 at 11:27 AM <gregkh@xxxxxxxxxxxxxxxxxxx> wrote:
>
>
> The patch below does not apply to the 4.19-stable tree.
> If someone wants it applied there, or to any other stable or longterm
> tree, then please email the backport, including the original git commit
> id to <stable@xxxxxxxxxxxxxxx>.
>
> thanks,
>
> greg k-h
>
> ------------------ original commit in Linus's tree ------------------
>
> From 360fe725f8849aaddc53475fef5d4a0c439b05ae Mon Sep 17 00:00:00 2001
> From: Huacai Chen <chenhc@xxxxxxxxxx>
> Date: Wed, 5 Sep 2018 17:33:09 +0800
> Subject: [PATCH] MIPS: Loongson-3: Fix BRIDGE irq delivery problem
>
> After commit e509bd7da149dc349160 ("genirq: Allow migration of chained
> interrupts by installing default action") Loongson-3 fails at here:
>
> setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
>
> This is because both chained_action and cascade_irqaction don't have
> IRQF_SHARED flag. This will cause Loongson-3 resume fails because HPET
> timer interrupt can't be delivered during S3. So we set the irqchip of
> the chained irq to loongson_irq_chip which doesn't disable the chained
> irq in CP0.Status.
>
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Huacai Chen <chenhc@xxxxxxxxxx>
> Signed-off-by: Paul Burton <paul.burton@xxxxxxxx>
> Patchwork: https://patchwork.linux-mips.org/patch/20434/
> Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
> Cc: James Hogan <jhogan@xxxxxxxxxx>
> Cc: linux-mips@xxxxxxxxxxxxxx
> Cc: Fuxin Zhang <zhangfx@xxxxxxxxxx>
> Cc: Zhangjin Wu <wuzhangjin@xxxxxxxxx>
> Cc: Huacai Chen <chenhuacai@xxxxxxxxx>
>
> diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
> index 3644b68c0ccc..be9f727a9328 100644
> --- a/arch/mips/include/asm/mach-loongson64/irq.h
> +++ b/arch/mips/include/asm/mach-loongson64/irq.h
> @@ -10,7 +10,7 @@
> #define MIPS_CPU_IRQ_BASE 56
>
> #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
> -#define LOONGSON_HT1_IRQ (MIPS_CPU_IRQ_BASE + 3) /* HT1 */
> +#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */
> #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
>
> #define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base
> diff --git a/arch/mips/loongson64/loongson-3/irq.c b/arch/mips/loongson64/loongson-3/irq.c
> index 2e115ab66a00..5605061f5f98 100644
> --- a/arch/mips/loongson64/loongson-3/irq.c
> +++ b/arch/mips/loongson64/loongson-3/irq.c
> @@ -96,12 +96,6 @@ void mach_irq_dispatch(unsigned int pending)
> }
> }
>
> -static struct irqaction cascade_irqaction = {
> - .handler = no_action,
> - .flags = IRQF_NO_SUSPEND,
> - .name = "cascade",
> -};
> -
> static inline void mask_loongson_irq(struct irq_data *d) { }
> static inline void unmask_loongson_irq(struct irq_data *d) { }
>
> @@ -147,11 +141,10 @@ void __init mach_init_irq(void)
>
> irq_set_chip_and_handler(LOONGSON_UART_IRQ,
> &loongson_irq_chip, handle_percpu_irq);
> + irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ,
> + &loongson_irq_chip, handle_percpu_irq);
>
> - /* setup HT1 irq */
> - setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
> -
> - set_c0_status(STATUSF_IP2 | STATUSF_IP6);
> + set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6);
> }
>
> #ifdef CONFIG_HOTPLUG_CPU
>
