Hi Greg,
This was not marked for stable but seems it should be in stable.
Please apply to your queue of 4.14-stable.
--
Regards
Sudip
>From 0b08b65ad657c08a9b8468d64624f6df52a2f863 Mon Sep 17 00:00:00 2001
From: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx>
Date: Thu, 24 May 2018 17:23:41 +1200
Subject: [PATCH] clk: mvebu: use correct bit for 98DX3236 NAND
commit 00c5a926af12a9f0236928dab3dc9faf621406a1 upstream
The correct fieldbit value for the NAND PLL reload trigger is 27.
Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC")
Signed-off-by: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx>
Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx>
Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@xxxxxxxxx>
---
drivers/clk/mvebu/clk-corediv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
index 8491979f4096..68f05c53d40e 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -72,7 +72,7 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = {
};
static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = {
- { .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */
+ { .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */
};
#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
--
2.11.0
