This is a note to let you know that I've just added the patch titled
ARM: sa11x0/assabet: ensure CS2 is configured appropriately
to the 3.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm-sa11x0-assabet-ensure-cs2-is-configured-appropriately.patch
and it can be found in the queue-3.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From f3964fe1c9d9a887d65faf594669852e4dec46e0 Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@xxxxxxxxxxxxxxxx>
Date: Wed, 16 Oct 2013 00:09:02 +0100
Subject: ARM: sa11x0/assabet: ensure CS2 is configured appropriately
From: Russell King <rmk+kernel@xxxxxxxxxxxxxxxx>
commit f3964fe1c9d9a887d65faf594669852e4dec46e0 upstream.
The CS2 region contains the Assabet board configuration and status
registers, which are 32-bit. Unfortunately, some boot loaders do not
configure this region correctly, leaving it setup as a 16-bit region.
Fix this.
Signed-off-by: Russell King <rmk+kernel@xxxxxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/arm/mach-sa1100/assabet.c | 3 +++
1 file changed, 3 insertions(+)
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -509,6 +509,9 @@ static void __init assabet_map_io(void)
* Its called GPCLKR0 in my SA1110 manual.
*/
Ser1SDCR0 |= SDCR0_SUS;
+ MSC1 = (MSC1 & ~0xffff) |
+ MSC_NonBrst | MSC_32BitStMem |
+ MSC_RdAcc(2) | MSC_WrAcc(2) | MSC_Rec(0);
if (!machine_has_neponset())
sa1100_register_uart_fns(&assabet_port_fns);
Patches currently in stable-queue which might be from rmk+kernel@xxxxxxxxxxxxxxxx are
queue-3.4/arm-sa11x0-assabet-ensure-cs2-is-configured-appropriately.patch
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