From: Ryder Lee <ryder.lee@xxxxxxxxxxxx>
[ Upstream commit 2b519747ae4859e886c37834d766fe0c7d8d82e2 ]
The input clock of UART0 should be CLK_PERI_UART0_PD.
Fixes: 13f36c326cef ("arm64: dts: mt7622: turn uart0 clock to real ones")
Signed-off-by: Ryder Lee <ryder.lee@xxxxxxxxxxxx>
Signed-off-by: Matthias Brugger <matthias.bgg@xxxxxxxxx>
Signed-off-by: Sasha Levin <alexander.levin@xxxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 9213c966c224..ec7ea8dca777 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -331,7 +331,7 @@
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&pericfg CLK_PERI_UART1_PD>;
+ <&pericfg CLK_PERI_UART0_PD>;
clock-names = "baud", "bus";
status = "disabled";
};
--
2.17.1
