On Thu, Sep 13, 2018 at 9:48 AM Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> wrote: > > 4.14-stable review patch. If anyone has any objections, please let me know. > > ------------------ > > From: Juergen Gross <jgross@xxxxxxxx> > > commit b2d7a075a1ccef2fb321d595802190c8e9b39004 upstream. > > Using only 32-bit writes for the pte will result in an intermediate > L1TF vulnerable PTE. When running as a Xen PV guest this will at once > switch the guest to shadow mode resulting in a loss of performance. > > Use arch_atomic64_xchg() instead which will perform the requested > operation atomically with all 64 bits. > > Some performance considerations according to: > > https://software.intel.com/sites/default/files/managed/ad/dc/Intel-Xeon-Scalable-Processor-throughput-latency.pdf > > The main number should be the latency, as there is no tight loop around > native_ptep_get_and_clear(). > > "lock cmpxchg8b" has a latency of 20 cycles, while "lock xchg" (with a > memory operand) isn't mentioned in that document. "lock xadd" (with xadd > having 3 cycles less latency than xchg) has a latency of 11, so we can > assume a latency of 14 for "lock xchg". > > Signed-off-by: Juergen Gross <jgross@xxxxxxxx> > Reviewed-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx> > Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx> > Tested-by: Jason Andryuk <jandryuk@xxxxxxxxx> > Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx> > Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> > > --- > arch/x86/include/asm/pgtable-3level.h | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > --- a/arch/x86/include/asm/pgtable-3level.h > +++ b/arch/x86/include/asm/pgtable-3level.h > @@ -2,6 +2,8 @@ > #ifndef _ASM_X86_PGTABLE_3LEVEL_H > #define _ASM_X86_PGTABLE_3LEVEL_H > > +#include <asm/atomic64_32.h> > + > /* > * Intel Physical Address Extension (PAE) Mode - three-level page > * tables on PPro+ CPUs. > @@ -147,10 +149,7 @@ static inline pte_t native_ptep_get_and_ > { > pte_t res; > > - /* xchg acts as a barrier before the setting of the high bits */ > - res.pte_low = xchg(&ptep->pte_low, 0); > - res.pte_high = ptep->pte_high; > - ptep->pte_high = 0; > + res.pte = (pteval_t)arch_atomic64_xchg((atomic64_t *)ptep, 0); For 4.14, I had to change this to atomic64_xchg since arch_atomic64_xchg doesn't exist. kernel-source/arch/x86/include/asm/pgtable-3level.h:152:22: error: implicit declaration of function 'arch_atomic64_xchg' [-Werror=implicit-function-declaration] The same is probably needed for earlier versions as well. Regards, Jason > > return res; > } > >
