On Wed, 12 Sep 2018, gregkh@xxxxxxxxxxxxxxxxxxx wrote:
> The patch below does not apply to the 4.19-stable tree.
Err what? There's no v4.19 stable release yet and the commit in question
is in v4.19-rc1. Did I miss a memo?
BR,
Jani.
> If someone wants it applied there, or to any other stable or longterm
> tree, then please email the backport, including the original git commit
> id to <stable@xxxxxxxxxxxxxxx>.
>
> thanks,
>
> greg k-h
>
> ------------------ original commit in Linus's tree ------------------
>
> From 6209c285e7a5e68dbcdf8fd2456c6dd68433806b Mon Sep 17 00:00:00 2001
> From: Jani Nikula <jani.nikula@xxxxxxxxx>
> Date: Tue, 14 Aug 2018 09:00:01 +0300
> Subject: [PATCH] drm/i915: set DP Main Stream Attribute for color range on DDI
> platforms
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
>
> Since Haswell we have no color range indication either in the pipe or
> port registers for DP. Instead, there's a separate register for setting
> the DP Main Stream Attributes (MSA) directly. The MSA register
> definition makes no references to colorimetry, just a vague reference to
> the DP spec. The connection to the color range was lost.
>
> Apparently we've failed to set the proper MSA bit for limited, or CEA,
> range ever since the first DDI platforms. We've started setting other
> MSA parameters since commit dae847991a43 ("drm/i915: add
> intel_ddi_set_pipe_settings").
>
> Without the crucial bit of information, the DP sink has no way of
> knowing the source is actually transmitting limited range RGB, leading
> to "washed out" colors. With the colorimetry information, compliant
> sinks should be able to handle the limited range properly. Native
> (i.e. non-LSPCON) HDMI was not affected because we do pass the color
> range via AVI infoframes.
>
> Though not the root cause, the problem was made worse for DDI platforms
> with commit 55bc60db5988 ("drm/i915: Add "Automatic" mode for the
> "Broadcast RGB" property"), which selects limited range RGB
> automatically based on the mode, as per the DP, HDMI and CEA specs.
>
> After all these years, the fix boils down to flipping one bit.
>
> [Per testing reports, this fixes DP sinks, but not the LSPCON. My
> educated guess is that the LSPCON fails to turn the CEA range MSA into
> AVI infoframes for HDMI.]
>
> Reported-by: Michał Kopeć <mkopec12@xxxxxxxxx>
> Reported-by: N. W. <nw9165-3201@xxxxxxxxx>
> Reported-by: Nicholas Stommel <nicholas.stommel@xxxxxxxxx>
> Reported-by: Tom Yan <tom.ty89@xxxxxxxxx>
> Tested-by: Nicholas Stommel <nicholas.stommel@xxxxxxxxx>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=100023
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107476
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=94921
> Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: <stable@xxxxxxxxxxxxxxx> # v3.9+
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> Link: https://patchwork.freedesktop.org/patch/msgid/20180814060001.18224-1-jani.nikula@xxxxxxxxx
> (cherry picked from commit dc5977da99ea28094b8fa4e9bacbd29bedc41de5)
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 91e7483228e1..08ec7446282e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9201,6 +9201,7 @@ enum skl_power_gate {
> #define TRANS_MSA_10_BPC (2 << 5)
> #define TRANS_MSA_12_BPC (3 << 5)
> #define TRANS_MSA_16_BPC (4 << 5)
> +#define TRANS_MSA_CEA_RANGE (1 << 3)
>
> /* LCPLL Control */
> #define LCPLL_CTL _MMIO(0x130040)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 39d66f8493fa..8761513f3532 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1685,6 +1685,10 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
> WARN_ON(transcoder_is_dsi(cpu_transcoder));
>
> temp = TRANS_MSA_SYNC_CLK;
> +
> + if (crtc_state->limited_color_range)
> + temp |= TRANS_MSA_CEA_RANGE;
> +
> switch (crtc_state->pipe_bpp) {
> case 18:
> temp |= TRANS_MSA_6_BPC;
>
--
Jani Nikula, Intel Open Source Graphics Center
