On Thu, Aug 9, 2018 at 1:19 AM, Icenowy Zheng <icenowy@xxxxxxx> wrote: > The bus clocks (AHB/APB) on Allwinner H6 have their second divider start > at bit 8, according to the user manual and the BSP code. However, > currently the divider is wrongly set to 16, thus the divider is not > correctly read and the clock frequency is not correctly calculated. > > Fix this bit offset on all affected bus clocks in ccu-sun50i-h6. > > Cc: stable@xxxxxxxxxxxxxxx # v4.17.y > Signed-off-by: Icenowy Zheng <icenowy@xxxxxxx> APB1 seems to be the only affected bus. Since there aren't any users ATM, I've queued this up for 4.20, with a few minor tweaks to the commit log: - s/wrongly/incorrectly/ - subject changed to "clk: sunxi-ng: h6: fix bus clocks' divider position" - third line: currently the divider _offset_ is ... ChenYu
