Hi, Bjorn Helgaas <bhelgaas@xxxxxxxxxx> writes: >> Bjorn Helgaas <helgaas@xxxxxxxxxx> writes: >> > On Fri, Aug 03, 2018 at 09:51:20AM +0300, Felipe Balbi wrote: >> >> Even thhough commit b891b4dc1eed claimed that original bit definitions >> >> were wrong, that's not really the case. After verifying PCI >> >> Specification Revisions 3.0, 3.1 and 4.0, Link Capabilites 2 >> >> Register's bit definitions were always starting from Bit 0. >> >> >> >> This has been causing issues reporting correct link speeds on sysfs. >> > >> > Can you elaborate on this a bit? b891b4dc1eed still looks correct to >> > me. I'm looking at PCIe r4.0, sec 7.5.3.18, where it shows: >> > >> > bit 0 RsvdP >> > bits 7:1 Supported Link Speeds Vector >> >> I had missed this detail, actually. It was a misinterpretation of the >> spec. Sorry for the noise. > > No problem. You were seeing something incorrect in sysfs, so if we > can help diagnose or fix whatever the real problem is, don't hesitate > to ask! Sure thing, but I think this is a problem elsewhere :) -- balbi
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