4.17-stable review patch. If anyone has any objections, please let me know.
------------------
From: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
[ Upstream commit 45ba63a29fd9b8a461110185e3abc5b4c90b806a ]
When the main processor goes idle, by default its clock is stopped.
However, this also stops the clock of the co-processor.
Here, if the C1CLK clock is enabled, we disable this functionality.
Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx>
Signed-off-by: Sasha Levin <alexander.levin@xxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/clk/ingenic/jz4770-cgu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -194,9 +194,10 @@ static const struct ingenic_cgu_clk_info
.div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 },
},
[JZ4770_CLK_C1CLK] = {
- "c1clk", CGU_CLK_DIV,
+ "c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4770_CLK_PLL0, },
.div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
+ .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
},
[JZ4770_CLK_PCLK] = {
"pclk", CGU_CLK_DIV,
