On 06/21/2018 01:27 PM, Thor Thayer wrote:
> Hi Dinh,
>
> On 05/29/2018 01:08 PM, thor.thayer@xxxxxxxxxxxxxxx wrote:
>> From: Thor Thayer <thor.thayer@xxxxxxxxxxxxxxx>
>>
>> Remove the unused bus-num node and change num-chipselect
>> to num-cs to match SPI bindings.
>>
>> Fixes: f2d6f8f817814 ("ARM: dts: socfpga: Add SPI Master1 for Arria10
>> SR chip")
>> Signed-off-by: Thor Thayer <thor.thayer@xxxxxxxxxxxxxxx>
>> Cc: stable@xxxxxxxxxxxxxxx
>> ---
>> arch/arm/boot/dts/socfpga_arria10.dtsi | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
>> b/arch/arm/boot/dts/socfpga_arria10.dtsi
>> index bead79e4b2aa..9138f834bad4 100644
>> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
>> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
>> @@ -593,8 +593,7 @@
>> #size-cells = <0>;
>> reg = <0xffda5000 0x100>;
>> interrupts = <0 102 4>;
>> - num-chipselect = <4>;
>> - bus-num = <0>;
>> + num-cs = <4>;
>> /*32bit_access;*/
>> tx-dma-channel = <&pdma 16>;
>> rx-dma-channel = <&pdma 17>;
>>
> Any update on this patch?
I've applied both patches.
Thanks,
Dinh
