On Fri, Jun 22, 2018 at 04:23:45PM +0100, Will Deacon wrote: > When rewriting swapper using nG mappings, we must performance cache > maintenance around each page table access in order to avoid coherency > problems with the host's cacheable alias under KVM. To ensure correct > ordering of the maintenance with respect to Device memory accesses made > with the Stage-1 MMU disabled, DMBs need to be added between the > maintenance and the corresponding memory access. > > This patch adds a missing DMB between writing a new page table entry and > performing a clean+invalidate on the same line. > > Cc: <stable@xxxxxxxxxxxxxxx> > Signed-off-by: Will Deacon <will.deacon@xxxxxxx> Applied. Thanks. -- Catalin
