3.16.57-rc1 review patch. If anyone has any objections, please let me know. ------------------ From: David Woodhouse <dwmw@xxxxxxxxxxxx> commit fc67dd70adb711a45d2ef34e12d1a8be75edde61 upstream. Add three feature bits exposed by new microcode on Intel CPUs for speculation control. Signed-off-by: David Woodhouse <dwmw@xxxxxxxxxxxx> Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx> Reviewed-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> Reviewed-by: Borislav Petkov <bp@xxxxxxx> Cc: gnomes@xxxxxxxxxxxxxxxxxxx Cc: ak@xxxxxxxxxxxxxxx Cc: ashok.raj@xxxxxxxxx Cc: dave.hansen@xxxxxxxxx Cc: karahmed@xxxxxxxxx Cc: arjan@xxxxxxxxxxxxxxx Cc: torvalds@xxxxxxxxxxxxxxxxxxxx Cc: peterz@xxxxxxxxxxxxx Cc: bp@xxxxxxxxx Cc: pbonzini@xxxxxxxxxx Cc: tim.c.chen@xxxxxxxxxxxxxxx Cc: gregkh@xxxxxxxxxxxxxxxxxxxx Link: https://lkml.kernel.org/r/1516896855-7642-3-git-send-email-dwmw@xxxxxxxxxxxx Signed-off-by: David Woodhouse <dwmw@xxxxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> [bwh: Backported to 3.16: This CPUID word wasn't used at all yet, so add it as feature word 10] Signed-off-by: Ben Hutchings <ben@xxxxxxxxxxxxxxx> --- arch/x86/include/asm/cpufeature.h | 7 ++++++- arch/x86/kernel/cpu/common.c | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -8,7 +8,7 @@ #include <asm/required-features.h> #endif -#define NCAPINTS 10 /* N 32-bit words worth of info */ +#define NCAPINTS 11 /* N 32-bit words worth of info */ #define NBUGINTS 1 /* N 32-bit bug flags */ /* @@ -234,6 +234,11 @@ #define X86_FEATURE_AVX512ER (9*32+27) /* AVX-512 Exponential and Reciprocal */ #define X86_FEATURE_AVX512CD (9*32+28) /* AVX-512 Conflict Detection */ +/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 10 */ +#define X86_FEATURE_SPEC_CTRL (10*32+26) /* Speculation Control (IBRS + IBPB) */ +#define X86_FEATURE_STIBP (10*32+27) /* Single Thread Indirect Branch Predictors */ +#define X86_FEATURE_ARCH_CAPABILITIES (10*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ + /* * BUG word(s) */ --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -701,6 +701,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); c->x86_capability[9] = ebx; + c->x86_capability[10] = edx; } /* AMD-defined flags: level 0x80000001 */
