3.16.57-rc1 review patch. If anyone has any objections, please let me know. ------------------ From: David Woodhouse <dwmw@xxxxxxxxxxxx> commit 5d10cbc91d9eb5537998b65608441b592eec65e7 upstream. AMD exposes the PRED_CMD/SPEC_CTRL MSRs slightly differently to Intel. See http://lkml.kernel.org/r/2b3e25cc-286d-8bd0-aeaf-9ac4aae39de8@xxxxxxx Signed-off-by: David Woodhouse <dwmw@xxxxxxxxxxxx> Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx> Reviewed-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> Cc: Tom Lendacky <thomas.lendacky@xxxxxxx> Cc: gnomes@xxxxxxxxxxxxxxxxxxx Cc: ak@xxxxxxxxxxxxxxx Cc: ashok.raj@xxxxxxxxx Cc: dave.hansen@xxxxxxxxx Cc: karahmed@xxxxxxxxx Cc: arjan@xxxxxxxxxxxxxxx Cc: torvalds@xxxxxxxxxxxxxxxxxxxx Cc: peterz@xxxxxxxxxxxxx Cc: bp@xxxxxxxxx Cc: pbonzini@xxxxxxxxxx Cc: tim.c.chen@xxxxxxxxxxxxxxx Cc: gregkh@xxxxxxxxxxxxxxxxxxxx Link: https://lkml.kernel.org/r/1516896855-7642-4-git-send-email-dwmw@xxxxxxxxxxxx Signed-off-by: David Woodhouse <dwmw@xxxxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> [bwh: Backported to 3.16: This CPUID word wasn't used at all yet, so add it as feature word 11] Signed-off-by: Ben Hutchings <ben@xxxxxxxxxxxxxxx> --- arch/x86/include/asm/cpufeature.h | 7 ++++++- arch/x86/kernel/cpu/common.c | 5 ++++- 2 files changed, 10 insertions(+), 2 deletions(-) --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -8,7 +8,7 @@ #include <asm/required-features.h> #endif -#define NCAPINTS 11 /* N 32-bit words worth of info */ +#define NCAPINTS 12 /* N 32-bit words worth of info */ #define NBUGINTS 1 /* N 32-bit bug flags */ /* @@ -239,6 +239,11 @@ #define X86_FEATURE_STIBP (10*32+27) /* Single Thread Indirect Branch Predictors */ #define X86_FEATURE_ARCH_CAPABILITIES (10*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ +/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 11 */ +#define X86_FEATURE_AMD_PRED_CMD (11*32+12) /* Prediction Command MSR (AMD) */ +#define X86_FEATURE_AMD_SPEC_CTRL (11*32+14) /* Speculation Control MSR only (AMD) */ +#define X86_FEATURE_AMD_STIBP (11*32+15) /* Single Thread Indirect Branch Predictors (AMD) */ + /* * BUG word(s) */ --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -716,10 +716,13 @@ void get_cpu_cap(struct cpuinfo_x86 *c) } if (c->extended_cpuid_level >= 0x80000008) { - u32 eax = cpuid_eax(0x80000008); + u32 eax, ebx, ecx, edx; + + cpuid(0x80000008, &eax, &ebx, &ecx, &edx); c->x86_virt_bits = (eax >> 8) & 0xff; c->x86_phys_bits = eax & 0xff; + c->x86_capability[11] = ebx; } #ifdef CONFIG_X86_32 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
