Hi Abhishek,
On Fri, 25 May 2018 17:51:35 +0530, Abhishek Sahu
<absahu@xxxxxxxxxxxxxx> wrote:
> The BAM has 3 channels - tx, rx and command. command channel
> is used for register read/writes, tx channel for data writes
> and rx channel for data reads. Currently, the driver assumes the
> transfer completion once it gets all the command descriptors
> completed. Sometimes, there is race condition between data channel
> (tx/rx) and command channel completion. In these cases,
> the data present in buffer is not valid during small window
> between command descriptor completion and data descriptor
> completion.
>
> This patch generates NAND transfer completion when both
> (Data and Command) DMA channels have completed all its DMA
> descriptors. It assigns completion callback in last
> DMA descriptors of that channel and wait for completion.
>
> Fixes: 8d6b6d7e135e ("mtd: nand: qcom: support for command descriptor formation")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Abhishek Sahu <absahu@xxxxxxxxxxxxxx>
> ---
> * Changes from v2:
> 1. Changed commit message and comments slightly
> 2. Renamed wait_second_completion from first_chan_done and set
> it before submit desc
> 3. Mark for stable tree
>
> * Changes from v1:
> NONE
>
> drivers/mtd/nand/raw/qcom_nandc.c | 53 ++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 52 insertions(+), 1 deletion(-)
>
Acked-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
