4.16-stable review patch. If anyone has any objections, please let me know.
------------------
From: Yixun Lan <yixun.lan@xxxxxxxxxxx>
[ Upstream commit 2fa9b361e500a0e092a9525afbd6a3a363ffa5f0 ]
According to the datasheet, the od shift of sys_pll is actually 16.
Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers')
Signed-off-by: Yixun Lan <yixun.lan@xxxxxxxxxxx>
[fixed commit message]
Signed-off-by: Jerome Brunet <jbrunet@xxxxxxxxxxxx>
Signed-off-by: Sasha Levin <alexander.levin@xxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/clk/meson/axg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -151,7 +151,7 @@ static struct meson_clk_pll axg_sys_pll
},
.od = {
.reg_off = HHI_SYS_PLL_CNTL,
- .shift = 10,
+ .shift = 16,
.width = 2,
},
.rate_table = sys_pll_rate_table,
