On Mon, Apr 23, 2018 at 04:58:43PM +0300, Imre Deak wrote:
> commit 5e1df40f40ee45a97bb1066c3d71f0ae920a9672 upstream.
>
> Currently we see sporadic timeouts during CDCLK changing both on BXT and
> GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by
> changing the frequency in a tight loop after blanking the display. The
> upper bound for the completion time is 800us based on my tests, so
> increase it from the current 500us to 2ms; with that I couldn't trigger
> the problem either on BXT or GLK.
>
> Note that timeouts happened during both the change notification and the
> voltage level setting PCODE request. (For the latter one BSpec doesn't
> require us to wait for completion before further HW programming.)
>
> This issue is similar to
> commit 2c7d0602c815 ("drm/i915/gen9: Fix PCODE polling during CDCLK
> change notification")
> but there the PCODE request does complete (as shown by the mbox
> busy flag), only the reply we get from PCODE indicates a failure.
> So there we keep resending the request until a success reply, here we
> just have to increase the timeout for the one PCODE request we send.
>
> v2:
> - s/snb_pcode_request/sandybridge_pcode_write_timeout/ (Ville)
>
> Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: <stable@xxxxxxxxxxxxxxx> # v4.15
> Acked-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> (v1)
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103326
> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> Link: https://patchwork.freedesktop.org/patch/msgid/20180130142939.17983-1-imre.deak@xxxxxxxxx
> (cherry picked from commit e76019a81921e87a4d9e7b3d86102bc708a6c227)
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> (Rebased for v4.15 stable tree due to upstream s/DIV_ROUND_UP(cdclk, 25000)/cdclk_state->voltage_level/ change )
4.15.y is end-of-life, sorry, so there's nothing I can do here.
greg k-h