4.9-stable review patch. If anyone has any objections, please let me know. ------------------ From: Koen Vandeputte <koen.vandeputte@xxxxxxxxxxxx> commit fc110ebdd014dd1368c98e7685b47789c31fab42 upstream. The subordinate value indicates the highest bus number which can be reached downstream though a certain device. Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in parent") ensures that downstream devices cannot assign busnumbers higher than the upstream device subordinate number, which was indeed illogical. By default, dw_pcie_setup_rc() inits the Root Complex subordinate to a value of 0x01. Due to this combined with above commit, enumeration stops digging deeper downstream as soon as bus num 0x01 has been assigned, which is always the case for a bridge device. This results in all devices behind a bridge bus remaining undetected, as these would be connected to bus 0x02 or higher. Fix this by initializing the RC to a subordinate value of 0xff, which is not altering hardware behaviour in any way, but informs probing function pci_scan_bridge() later on which reads this value back from register. The following nasty errors during boot are also fixed by this: pci_bus 0000:02: busn_res: can not insert [bus 02-ff] under [bus 01] (conflicts with (null) [bus 01]) ... pci_bus 0000:03: [bus 03] partially hidden behind bridge 0000:01 [bus 01] ... pci_bus 0000:04: [bus 04] partially hidden behind bridge 0000:01 [bus 01] ... pci_bus 0000:05: [bus 05] partially hidden behind bridge 0000:01 [bus 01] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 05 pci_bus 0000:02: busn_res: can not insert [bus 02-05] under [bus 01] (conflicts with (null) [bus 01]) pci_bus 0000:02: [bus 02-05] partially hidden behind bridge 0000:01 [bus 01] Fixes: a20c7f36bd3d ("PCI: Do not allocate more buses than available in parent") Tested-by: Niklas Cassel <niklas.cassel@xxxxxxxx> Tested-by: Fabio Estevam <fabio.estevam@xxxxxxx> Tested-by: Sebastian Reichel <sebastian.reichel@xxxxxxxxxxxxxxx> Signed-off-by: Koen Vandeputte <koen.vandeputte@xxxxxxxxxxxx> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx> Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> Reviewed-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx> Acked-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> Cc: stable@xxxxxxxxxxxxxxx # v4.15+ Cc: Binghui Wang <wangbinghui@xxxxxxxxxxxxx> Cc: Jesper Nilsson <jesper.nilsson@xxxxxxxx> Cc: Jianguo Sun <sunjianguo1@xxxxxxxxxx> Cc: Jingoo Han <jingoohan1@xxxxxxxxx> Cc: Kishon Vijay Abraham I <kishon@xxxxxx> Cc: Lucas Stach <l.stach@xxxxxxxxxxxxxx> Cc: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx> Cc: Minghuan Lian <minghuan.Lian@xxxxxxxxxxxxx> Cc: Mingkai Hu <mingkai.hu@xxxxxxxxxxxxx> Cc: Murali Karicheri <m-karicheri2@xxxxxx> Cc: Pratyush Anand <pratyush.anand@xxxxxxxxx> Cc: Richard Zhu <hongxing.zhu@xxxxxxx> Cc: Roy Zang <tie-fei.zang@xxxxxxxxxxxxx> Cc: Shawn Guo <shawn.guo@xxxxxxxxxx> Cc: Stanimir Varbanov <svarbanov@xxxxxxxxxx> Cc: Thomas Petazzoni <thomas.petazzoni@xxxxxxxxxxxxxxxxxx> Cc: Xiaowei Song <songxiaowei@xxxxxxxxxxxxx> Cc: Zhou Wang <wangzhou1@xxxxxxxxxxxxx> [fabio: adapted to the file location of 4.9 kernel] Signed-off-by: Fabio Estevam <fabio.estevam@xxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/pci/host/pcie-designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -861,7 +861,7 @@ void dw_pcie_setup_rc(struct pcie_port * /* setup bus numbers */ val = dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS); val &= 0xff000000; - val |= 0x00010100; + val |= 0x00ff0100; dw_pcie_writel_rc(pp, PCI_PRIMARY_BUS, val); /* setup command register */