Patch "drm/radeon: update line buffer allocation for dce4.1/5" has been added to the 3.11-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/radeon: update line buffer allocation for dce4.1/5

to the 3.11-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-radeon-update-line-buffer-allocation-for-dce4.1-5.patch
and it can be found in the queue-3.11 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.


>From 0b31e02363b0db4e7931561bc6c141436e729d9f Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@xxxxxxx>
Date: Mon, 19 Aug 2013 11:06:50 -0400
Subject: drm/radeon: update line buffer allocation for dce4.1/5

From: Alex Deucher <alexander.deucher@xxxxxxx>

commit 0b31e02363b0db4e7931561bc6c141436e729d9f upstream.

We need to allocate line buffer to each display when
setting up the watermarks.  Failure to do so can lead
to a blank screen.  This fixes blank screen problems
on dce4.1/5 asics.

Based on an initial fix from:
Jay Cornwall <jay.cornwall@xxxxxxx>

Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>

---
 drivers/gpu/drm/radeon/evergreen.c  |   25 +++++++++++++++++++++----
 drivers/gpu/drm/radeon/evergreend.h |    4 ++++
 2 files changed, 25 insertions(+), 4 deletions(-)

--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1807,7 +1807,8 @@ static u32 evergreen_line_buffer_adjust(
 					struct drm_display_mode *mode,
 					struct drm_display_mode *other_mode)
 {
-	u32 tmp;
+	u32 tmp, buffer_alloc, i;
+	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
 	/*
 	 * Line Buffer Setup
 	 * There are 3 line buffers, each one shared by 2 display controllers.
@@ -1830,18 +1831,34 @@ static u32 evergreen_line_buffer_adjust(
 	 * non-linked crtcs for maximum line buffer allocation.
 	 */
 	if (radeon_crtc->base.enabled && mode) {
-		if (other_mode)
+		if (other_mode) {
 			tmp = 0; /* 1/2 */
-		else
+			buffer_alloc = 1;
+		} else {
 			tmp = 2; /* whole */
-	} else
+			buffer_alloc = 2;
+		}
+	} else {
 		tmp = 0;
+		buffer_alloc = 0;
+	}
 
 	/* second controller of the pair uses second half of the lb */
 	if (radeon_crtc->crtc_id % 2)
 		tmp += 4;
 	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 
+	if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
+		WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
+		       DMIF_BUFFERS_ALLOCATED(buffer_alloc));
+		for (i = 0; i < rdev->usec_timeout; i++) {
+			if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
+			    DMIF_BUFFERS_ALLOCATED_COMPLETED)
+				break;
+			udelay(1);
+		}
+	}
+
 	if (radeon_crtc->base.enabled && mode) {
 		switch (tmp) {
 		case 0:
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1153,6 +1153,10 @@
 #       define LATENCY_LOW_WATERMARK(x)                   ((x) << 0)
 #       define LATENCY_HIGH_WATERMARK(x)                  ((x) << 16)
 
+#define	PIPE0_DMIF_BUFFER_CONTROL			  0x0ca0
+#       define DMIF_BUFFERS_ALLOCATED(x)                  ((x) << 0)
+#       define DMIF_BUFFERS_ALLOCATED_COMPLETED           (1 << 4)
+
 #define IH_RB_CNTL                                        0x3e00
 #       define IH_RB_ENABLE                               (1 << 0)
 #       define IH_IB_SIZE(x)                              ((x) << 1) /* log2 */


Patches currently in stable-queue which might be from alexander.deucher@xxxxxxx are

queue-3.11/radeon-kms-fix-uninitialised-hotplug-work-usage-in-r100_irq_process.patch
queue-3.11/drm-radeon-fix-init-ordering-for-r600.patch
queue-3.11/drm-radeon-add-berlin-pci-ids.patch
queue-3.11/drm-radeon-enable-uvd-interrupts-on-cik.patch
queue-3.11/drm-radeon-fix-lcd-record-parsing.patch
queue-3.11/drm-radeon-fix-resume-on-some-rs4xx-boards-v2.patch
queue-3.11/drm-radeon-cik-update-gpu_init-for-an-additional-berlin-gpu.patch
queue-3.11/drm-radeon-update-line-buffer-allocation-for-dce8.patch
queue-3.11/drm-radeon-si-add-support-for-cp-dma-to-cs-checker-for-compute-v2.patch
queue-3.11/drm-radeon-fix-endian-bugs-in-hw-i2c-atom-routines.patch
queue-3.11/drm-radeon-dpm-add-reclocking-quirk-for-asus-k70af.patch
queue-3.11/drm-radeon-update-line-buffer-allocation-for-dce6.patch
queue-3.11/drm-radeon-update-line-buffer-allocation-for-dce4.1-5.patch
queue-3.11/drm-radeon-dpm-make-sure-dc-performance-level-limits-are-valid-btc-si-v2.patch
queue-3.11/drm-radeon-fix-handling-of-variable-sized-arrays-for-router-objects.patch
queue-3.11/drm-radeon-fill-in-gpu_init-for-berlin-gpu-cores.patch
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