Re: FAILED: patch "[PATCH] drm/i915: Disable MSI for all pre-gen5" failed to apply to 4.13-stable tree

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On Wed, Sep 20, 2017 at 6:17 AM,  <gregkh@xxxxxxxxxxxxxxxxxxx> wrote:
>
> The patch below does not apply to the 4.13-stable tree.
> If someone wants it applied there, or to any other stable or longterm
> tree, then please email the backport, including the original git commit
> id to <stable@xxxxxxxxxxxxxxx>.
>
> thanks,
>
> greg k-h
>
> ------------------ original commit in Linus's tree ------------------
>
> From e38c2da01f76cca82b59ca612529b81df82a7cc7 Mon Sep 17 00:00:00 2001
> From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@xxxxxxxxxxxxxxx>
> Date: Mon, 26 Jun 2017 23:30:51 +0300
> Subject: [PATCH] drm/i915: Disable MSI for all pre-gen5
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
>
> We have pretty clear evidence that MSIs are getting lost on g4x and
> somehow the interrupt logic doesn't seem to recover from that state
> even if we try hard to clear the IIR.
>
> Disabling IER around the normal IIR clearing in the irq handler isn't
> sufficient to avoid this, so the problem really seems to be further
> up the interrupt chain. This should guarantee that there's always
> an edge if any IIR bits are set after the interrupt handler is done,
> which should normally guarantee that the CPU interrupt is generated.
> That approach seems to work perfectly on VLV/CHV, but apparently
> not on g4x.
>
> MSI is documented to be broken on 965gm at least. The chipset spec
> says MSI is defeatured because interrupts can be delayed or lost,
> which fits well with what we're seeing on g4x. Previously we've
> already disabled GMBUS interrupts on g4x because somehow GMBUS
> manages to raise legacy interrupts even when MSI is enabled.
>
> Since there's such widespread MSI breakahge all over in the pre-gen5
> land let's just give up on MSI on these platforms.
>
> Seqno reporting might be negatively affected by this since the legcy
> interrupts aren't guaranteed to be ordered with the seqno writes,
> whereas MSI interrupts may be? But an occasioanlly missed seqno
> seems like a small price to pay for generally working interrupts.
>
> Cc: stable@xxxxxxxxxxxxxxx
> Cc: Diego Viola <diego.viola@xxxxxxxxx>
> Tested-by: Diego Viola <diego.viola@xxxxxxxxx>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101261
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Link: http://patchwork.freedesktop.org/patch/msgid/20170626203051.28480-1-ville.syrjala@xxxxxxxxxxxxxxx
> Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 43e925933688..a6bef9ee8703 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1141,10 +1141,12 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>          * and the registers being closely associated.
>          *
>          * According to chipset errata, on the 965GM, MSI interrupts may
> -        * be lost or delayed, but we use them anyways to avoid
> -        * stuck interrupts on some machines.
> +        * be lost or delayed, and was defeatured. MSI interrupts seem to
> +        * get lost on g4x as well, and interrupt delivery seems to stay
> +        * properly dead afterwards. So we'll just disable them for all
> +        * pre-gen5 chipsets.
>          */
> -       if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
> +       if (INTEL_GEN(dev_priv) >= 5) {
>                 if (pci_enable_msi(pdev) < 0)
>                         DRM_DEBUG_DRIVER("can't enable MSI");
>         }
>

Hi Greg,

This patch was already merged in torvalds/linux.git before 4.13 was
released, so it is already available in 4.13.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/i915/i915_drv.c?id=e38c2da01f76cca82b59ca612529b81df82a7cc7

Thanks,
Diego




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