On Fri, Sep 15, 2017 at 11:41 AM, Marek Szyprowski
<m.szyprowski@xxxxxxxxxxx> wrote:
> Commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for
> PLL36XX clocks") added enable/disable operations to PLL clocks. Prior that
> VPLL and EPPL clocks were always enabled because the enable bit was never
> touched. Those clocks have to be enabled during suspend/resume cycle,
> because otherwise board fails to enter sleep mode. This patch enables them
> unconditionally before entering system suspend state. System restore
> function will set them to the previous state saved in the register cache
> done before that unconditional enable.
>
> Fixes: 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks")
> CC: stable@xxxxxxxxxxxxxxx # v4.13
> Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
> ---
> Changelog:
> v2:
> - wait until PLL is properly locked
> ---
> drivers/clk/samsung/clk-exynos4.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
> index e40b77583c47..d8d3cb67b402 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -294,6 +294,18 @@ enum exynos4_plls {
> #define PLL_ENABLED (1 << 31)
> #define PLL_LOCKED (1 << 29)
>
> +static void exynos4_clk_enable_pll(u32 reg)
> +{
> + u32 pll_con = readl(reg_base + reg);
> + pll_con |= PLL_ENABLED;
> + writel(pll_con, reg_base + reg);
> +
> + while (!(pll_con & PLL_LOCKED)) {
> + cpu_relax();
> + pll_con = readl(reg_base + reg);
> + }
Looks good:
Reviewed-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx>
As a follow up for the fix (separate patch) we could consider adding
timeouts to both busy-loops (waiting on PLL_LOCKED). Also the busy
loop itself could be factored out (less code duplicate). However both
should not be part of this fix.
Best regards,
Krzysztof