On Thu, Jul 20, 2017 at 11:58:35AM +0300, Jani Nikula wrote: > On Thu, 20 Jul 2017, Imre Deak <imre.deak@xxxxxxxxx> wrote: > > The scaler allocation code depends on a non-zero default value for the > > crtc scaler_id, so make sure we initialize the scaler state accordingly > > even if the crtc is off. This fixes at least an initial YUV420 modeset > > (added in a follow-up patchset by Shashank) when booting with the screen > > off: after the initial HW readout and modeset which enables the scaler a > > subsequent modeset will disable the scaler which isn't properly > > allocated. This results in a funky HW state where the pipe scaler HW > > registers can't be modified and the normally black screen is grey and > > shifted to the right or jitters. > > > > The problem was revealed by Shashank's YUV420 patchset and first > > reported by Ville. > > > > Cc: Shashank Sharma <shashank.sharma@xxxxxxxxx> > > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Cc: Chandra Konduru <chandra.konduru@xxxxxxxxx> > > Cc: Matt Roper <matthew.d.roper@xxxxxxxxx> > > Cc: <stable@xxxxxxxxxxxxxxx> # 4.11.x > > Reported-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Fixes: a1b2278e4dfc ("drm/i915: skylake panel fitting using shared scalers") > > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> > > > > --- > > > > [ Older stable versions need backporting, so that's for a follow-up ] > > I thought we'd annotate cc: stable with all the kernels that need the > fix, not according to where the fix applies as-is. In this case, it > would be v4.2+, right? Hm, not sure. I know that this won't apply before 4.11 and I will have to send a backported version anyway. So wanted to save a redundant turn around after the automatic cherry picking to those stable versions fail. Greg, what's the proper tag in this case? Thanks, Imre > > BR, > Jani. > > > > > --- > > drivers/gpu/drm/i915/intel_display.c | 14 +++++++------- > > 1 file changed, 7 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index 7774f3465fbc..8a38e64b1931 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -9132,6 +9132,13 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > > u64 power_domain_mask; > > bool active; > > > > + if (INTEL_GEN(dev_priv) >= 9) { > > + intel_crtc_init_scalers(crtc, pipe_config); > > + > > + pipe_config->scaler_state.scaler_id = -1; > > + pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); > > + } > > + > > power_domain = POWER_DOMAIN_PIPE(crtc->pipe); > > if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) > > return false; > > @@ -9160,13 +9167,6 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > > pipe_config->gamma_mode = > > I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; > > > > - if (INTEL_GEN(dev_priv) >= 9) { > > - intel_crtc_init_scalers(crtc, pipe_config); > > - > > - pipe_config->scaler_state.scaler_id = -1; > > - pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); > > - } > > - > > power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); > > if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { > > power_domain_mask |= BIT_ULL(power_domain); > > -- > Jani Nikula, Intel Open Source Technology Center