Quoting ville.syrjala@xxxxxxxxxxxxxxx (2017-06-26 21:30:51) > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > We have pretty clear evidence that MSIs are getting lost on g4x and > somehow the interrupt logic doesn't seem to recover from that state > even if we try hard to clear the IIR. > > Disabling IER around the normal IIR clearing in the irq handler isn't > sufficient to avoid this, so the problem really seems to be further > up the interrupt chain. This should guarantee that there's always > an edge if any IIR bits are set after the interrupt handler is done, > which should normally guarantee that the CPU interrupt is generated. > That approach seems to work perfectly on VLV/CHV, but apparently > not on g4x. > > MSI is documented to be broken on 965gm at least. The chipset spec > says MSI is defeatured because interrupts can be delayed or lost, > which fits well with what we're seeing on g4x. Previously we've > already disabled GMBUS interrupts on g4x because somehow GMBUS > manages to raise legacy interrupts even when MSI is enabled. > > Since there's such widespread MSI breakahge all over in the pre-gen5 > land let's just give up on MSI on these platforms. An unmentioned sibling caught by this change is g33. It is very unlikely to have been fixed in g33 but broken in g4x, still deserves a mention as old gen3 used MSI and g33 tried to tame the beast. > Seqno reporting might be negatively affected by this since the legcy > interrupts aren't guaranteed to be ordered with the seqno writes, > whereas MSI interrupts may be? But an occasioanlly missed seqno > seems like a small price to pay for generally working interrupts. > > Cc: stable@xxxxxxxxxxxxxxx > Cc: Diego Viola <diego.viola@xxxxxxxxx> > Tested-by: Diego Viola <diego.viola@xxxxxxxxx> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101261 > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Acked-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris