Re: Patch "drm/amd/powerplay/smu7: add vblank check for mclk switching (v2)" has been added to the 4.9-stable tree

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Nope, breaks the build, so I dropped it from 4.9, if someone wants it
there, please provide a backport that works.

thanks,

greg k-h

On Mon, Jun 05, 2017 at 02:48:43PM +0200, gregkh@xxxxxxxxxxxxxxxxxxx wrote:
> 
> This is a note to let you know that I've just added the patch titled
> 
>     drm/amd/powerplay/smu7: add vblank check for mclk switching (v2)
> 
> to the 4.9-stable tree which can be found at:
>     http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
> 
> The filename of the patch is:
>      drm-amd-powerplay-smu7-add-vblank-check-for-mclk-switching-v2.patch
> and it can be found in the queue-4.9 subdirectory.
> 
> If you, or anyone else, feels it should not be added to the stable tree,
> please let <stable@xxxxxxxxxxxxxxx> know about it.
> 
> 
> >From 09be4a5219610a6fae3215d4f51f948d6f5d2609 Mon Sep 17 00:00:00 2001
> From: Alex Deucher <alexander.deucher@xxxxxxx>
> Date: Thu, 11 May 2017 13:46:12 -0400
> Subject: drm/amd/powerplay/smu7: add vblank check for mclk switching (v2)
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
> 
> From: Alex Deucher <alexander.deucher@xxxxxxx>
> 
> commit 09be4a5219610a6fae3215d4f51f948d6f5d2609 upstream.
> 
> Check to make sure the vblank period is long enough to support
> mclk switching.
> 
> v2: drop needless initial assignment (Nils)
> 
> bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868
> 
> Acked-by: Christian König <christian.koenig@xxxxxxx>
> Reviewed-by: Rex Zhu <Rex.Zhu@xxxxxxx>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
> 
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c |   31 ++++++++++++++++++++---
>  1 file changed, 27 insertions(+), 4 deletions(-)
> 
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -2495,6 +2495,28 @@ static int smu7_get_power_state_size(str
>  	return sizeof(struct smu7_power_state);
>  }
>  
> +static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
> +				 uint32_t vblank_time_us)
> +{
> +	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +	uint32_t switch_limit_us;
> +
> +	switch (hwmgr->chip_id) {
> +	case CHIP_POLARIS10:
> +	case CHIP_POLARIS11:
> +	case CHIP_POLARIS12:
> +		switch_limit_us = data->is_memory_gddr5 ? 190 : 150;
> +		break;
> +	default:
> +		switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
> +		break;
> +	}
> +
> +	if (vblank_time_us < switch_limit_us)
> +		return true;
> +	else
> +		return false;
> +}
>  
>  static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
>  				struct pp_power_state *request_ps,
> @@ -2509,6 +2531,7 @@ static int smu7_apply_state_adjust_rules
>  	bool disable_mclk_switching;
>  	bool disable_mclk_switching_for_frame_lock;
>  	struct cgs_display_info info = {0};
> +	struct cgs_mode_info mode_info = {0};
>  	const struct phm_clock_and_voltage_limits *max_limits;
>  	uint32_t i;
>  	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> @@ -2517,6 +2540,7 @@ static int smu7_apply_state_adjust_rules
>  	int32_t count;
>  	int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
>  
> +	info.mode_info = &mode_info;
>  	data->battery_state = (PP_StateUILabel_Battery ==
>  			request_ps->classification.ui_label);
>  
> @@ -2543,8 +2567,6 @@ static int smu7_apply_state_adjust_rules
>  
>  	cgs_get_active_displays_info(hwmgr->device, &info);
>  
> -	/*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
> -
>  	minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
>  	minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
>  
> @@ -2609,8 +2631,9 @@ static int smu7_apply_state_adjust_rules
>  				    PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
>  
>  
> -	disable_mclk_switching = (1 < info.display_count) ||
> -				    disable_mclk_switching_for_frame_lock;
> +	disable_mclk_switching = ((1 < info.display_count) ||
> +				  disable_mclk_switching_for_frame_lock ||
> +				  smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us));
>  
>  	sclk = smu7_ps->performance_levels[0].engine_clock;
>  	mclk = smu7_ps->performance_levels[0].memory_clock;
> 
> 
> Patches currently in stable-queue which might be from alexander.deucher@xxxxxxx are
> 
> queue-4.9/drm-amd-powerplay-smu7-add-vblank-check-for-mclk-switching-v2.patch
> queue-4.9/drm-radeon-fix-vram_size-visible-values-in-drm_radeon_gem_info-ioctl.patch
> queue-4.9/drm-radeon-ci-disable-mclk-switching-for-high-refresh-rates-v2.patch
> queue-4.9/drm-radeon-unbreak-hpd-handling-for-r600.patch
> queue-4.9/drm-amd-powerplay-smu7-disable-mclk-switching-for-high-refresh-rates.patch



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