This is a note to let you know that I've just added the patch titled
MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6
to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
mips-loongson-3-select-mips_l1_cache_shift_6.patch
and it can be found in the queue-4.9 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 17c99d9421695a0e0de18bf1e7091d859e20ec1d Mon Sep 17 00:00:00 2001
From: Huacai Chen <chenhc@xxxxxxxxxx>
Date: Thu, 16 Mar 2017 21:00:28 +0800
Subject: MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6
From: Huacai Chen <chenhc@xxxxxxxxxx>
commit 17c99d9421695a0e0de18bf1e7091d859e20ec1d upstream.
Some newer Loongson-3 have 64 bytes cache lines, so select
MIPS_L1_CACHE_SHIFT_6.
Signed-off-by: Huacai Chen <chenhc@xxxxxxxxxx>
Cc: John Crispin <john@xxxxxxxxxxx>
Cc: Steven J . Hill <Steven.Hill@xxxxxxxxxxxxxxxxxx>
Cc: Fuxin Zhang <zhangfx@xxxxxxxxxx>
Cc: Zhangjin Wu <wuzhangjin@xxxxxxxxx>
Cc: linux-mips@xxxxxxxxxxxxxx
Patchwork: https://patchwork.linux-mips.org/patch/15755/
Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1368,6 +1368,7 @@ config CPU_LOONGSON3
select WEAK_ORDERING
select WEAK_REORDERING_BEYOND_LLSC
select MIPS_PGD_C0_CONTEXT
+ select MIPS_L1_CACHE_SHIFT_6
select GPIOLIB
help
The Loongson 3 processor implements the MIPS64R2 instruction
Patches currently in stable-queue which might be from chenhc@xxxxxxxxxx are
queue-4.9/mips-loongson-3-select-mips_l1_cache_shift_6.patch