This is related to how how different asm instructions write to a bitfield member. In BE config, @orig_r8 is at offset 0 while @event is at offset 2. "ST 0xNNNN_EEEE, [addr]" correctly writes 0xEEEE to @event, however a half word write, "STW 0xEEEE, [addr]" does not in Big Endian while works perfectly file for LE config (since @event is at offset 0). ------>8--------------- Thi issue is already fixed in mainline 3.11 kernel as part of commit: 502a0c775c7f0a "ARC: pt_regs update #5" However that patch has lot more changes than I would like backporting, hence this seperate change. ------>8--------------- Reported-by: Noam Camus <noamc@xxxxxxxxxx> Cc: <stable@xxxxxxxxxxxxxxx> # [3.9 and 3.10 only] Tested-by: Anton Kolesov <akolesov@xxxxxxxxxxxx> Signed-off-by: Vineet Gupta <vgupta@xxxxxxxxxxxx> --- arch/arc/kernel/entry.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S index 7b5f3ec..724de08 100644 --- a/arch/arc/kernel/entry.S +++ b/arch/arc/kernel/entry.S @@ -498,7 +498,7 @@ tracesys_exit: trap_with_param: ; stop_pc info by gdb needs this info - stw orig_r8_IS_BRKPT, [sp, PT_orig_r8] + st orig_r8_IS_BRKPT, [sp, PT_orig_r8] mov r0, r12 lr r1, [efa] @@ -727,7 +727,7 @@ not_exception: ; things to what they were, before returning from L2 context ;---------------------------------------------------------------- - ldw r9, [sp, PT_orig_r8] ; get orig_r8 to make sure it is + ld r9, [sp, PT_orig_r8] ; get orig_r8 to make sure it is brne r9, orig_r8_IS_IRQ2, 149f ; infact a L2 ISR ret path ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs) -- 1.8.1.2 -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html