4.9-stable review patch. If anyone has any objections, please let me know. ------------------ From: Huacai Chen <chenhc@xxxxxxxxxx> commit 033cffeedbd11c140952b98e8639bf652091a17d upstream. Loongson-3A R2 and newer CPU have FTLB, but Config0.MT is 1, so add MIPS_CPU_FTLB to the CPU options. Signed-off-by: Huacai Chen <chenhc@xxxxxxxxxx> Cc: John Crispin <john@xxxxxxxxxxx> Cc: Steven J . Hill <Steven.Hill@xxxxxxxxxxxxxxxxxx> Cc: Fuxin Zhang <zhangfx@xxxxxxxxxx> Cc: Zhangjin Wu <wuzhangjin@xxxxxxxxx> Cc: linux-mips@xxxxxxxxxxxxxx Patchwork: https://patchwork.linux-mips.org/patch/15752/ Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- arch/mips/kernel/cpu-probe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1824,7 +1824,7 @@ static inline void cpu_probe_loongson(st } decode_configs(c); - c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; + c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; c->writecombine = _CACHE_UNCACHED_ACCELERATED; break; default: