Amit Pundir <amit.pundir@xxxxxxxxxx> writes: > From: Eric Anholt <eric@xxxxxxxxxx> > > Our core PLLs are intended to be configured once and left alone. With > the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would > change PLLD just to get closer to the requested DSI clock, thus > changing PLLD_PER, the UART and ethernet PHY clock rates downstream of > it, and breaking ethernet. > > We *do* want PLLH to change so that PLLH_AUX can be exactly the value > we want, though. Thus, we need to have a per-divider policy of > whether to pass rate changes up. I don't have the full series so I'm not sure why these 3 are being sent to stable, but they don't seem like stable candidates to me.
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