On 14/03/2017 at 09:38:04 +0100, Nicolas Ferre wrote:
> On some DDR controllers, compatible with the sama5d3 one,
> the sequence to enter/exit/re-enter the self-refresh mode adds
> more constrains than what is currently written in the at91_idle
> driver. An actual access to the DDR chip is needed between exit
> and re-enter of this mode which is somehow difficult to implement.
> This sequence can completely hang the SoC. It is particularly
> experienced on parts which embed a L2 cache if the code run
> between IDLE calls fits in it...
>
> Moreover, as the intention is to enter and exit pretty rapidly
> from IDLE, the power-down mode is a good candidate.
>
> So now we use power-down instead of self-refresh. As we can
> simplify the code for sama5d3 compatible DDR controllers,
> we instantiate a new sama5d3_ddr_standby() function.
>
> Signed-off-by: Nicolas Ferre <nicolas.ferre@xxxxxxxxxxxxx>
> Cc: <stable@xxxxxxxxxxxxxxx> # v4.1+
> Fixes: 017b5522d5e3 ("ARM: at91: Add new binding for sama5d3-ddramc")
Applied, thanks.
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com