Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes:
> Disable RPS by setting RP_CONTROL to 0, remembering its earlier value.
> Then adjust the thresholds before re-enabling RP_CONTROL.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx
Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d37e95b3525d..e5cfa0377367 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4804,6 +4804,7 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
> int new_power;
> u32 threshold_up = 0, threshold_down = 0; /* in % */
> u32 ei_up = 0, ei_down = 0;
> + u32 rp_control;
>
> new_power = dev_priv->rps.power;
> switch (dev_priv->rps.power) {
> @@ -4872,6 +4873,12 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
> spin_lock_irq(&dev_priv->uncore.lock);
> intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
>
> + /* Stop RPS before changing thresholds */
> + rp_control = I915_READ_FW(GEN6_RP_CONTROL);
> + I915_WRITE_FW(GEN6_RP_CONTROL, 0);
> + POSTING_READ_FW(GEN6_RP_CONTROL);
> +
> + /* Update thresholds and evaluation intervals */
> I915_WRITE_FW(GEN6_RP_UP_EI,
> GT_INTERVAL_FROM_US(dev_priv, ei_up));
> I915_WRITE_FW(GEN6_RP_UP_THRESHOLD,
> @@ -4885,8 +4892,7 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
> ei_down * threshold_down / 100));
>
> /* Restart RPS to reload the thresholds */
> - I915_WRITE_FW(GEN6_RP_CONTROL,
> - I915_READ_FW(GEN6_RP_CONTROL) | GEN6_RP_ENABLE);
> + I915_WRITE_FW(GEN6_RP_CONTROL, rp_control | GEN6_RP_ENABLE);
>
> intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
> spin_unlock_irq(&dev_priv->uncore.lock);
> --
> 2.11.0