3.16.40-rc1 review patch. If anyone has any objections, please let me know.
------------------
From: Krzysztof Kozlowski <k.kozlowski@xxxxxxxxxxx>
commit f7061ffb44116490f282f130a220ca2d10849248 upstream.
The pinctrl pull up/down register on exynos4210 is 2-bit wide for each
pin and it accepts only values of 0, 1 and 3. The pins sd4-bus-width8
were configured with value of 4. The driver does not validate the value
so this overflow effectively set a bit 1 in adjacent pins thus
configuring them to pull down.
The author's intention was probably to set drive strength of 4x. All
other bus-widths pins are configured with pull up and drive strength of
4x. Fix this one with same pattern.
Fixes: 87711d8c7c70 ("ARM: dts: Add pinctrl node entries for SAMSUNG EXYNOS4210 SoC")
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@xxxxxxxxxxx>
Reviewed-by: Javier Martinez Canillas <javier@xxxxxxxxxxxxxxx>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@xxxxxxxxxxx>
Acked-by: Linus Walleij <linus.walleij@xxxxxxxxxx>
[bwh: Backported to 3.16: use literal constant]
Signed-off-by: Ben Hutchings <ben@xxxxxxxxxxxxxxx>
---
arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -647,7 +647,7 @@
sd4_bus8: sd4-bus-width8 {
samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
samsung,pin-function = <3>;
- samsung,pin-pud = <4>;
+ samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};