On Fri, Oct 28, 2016 at 10:51:57AM -0500, Yazen Ghannam wrote:
> The current Fam17h cpu_llc_id derivation has an underflow bug when
^
(Last Level Cache ID)
Let's write it out the first time.
> extracting the socket_id value. The socket_id value starts from 0, so
> subtracting 1 will result in an underflow. This breaks scheduling topology
> later on since the cpu_llc_id will be incorrect.
>
> The apicid decoding is fixed for bits 3 and above,
^
"is fixed ... in register... "
> which give the core
> complex, node and socket IDs. The LLC is at the core complex level so we
> can find a unique cpu_llc_id by right shifting the apicid by 3.
"... because then the LSBit will be the Core Complex ID."
> We can fix the underflow bug and simplify the code by replacing the
> current cpu_llc_id derivation with a right shift.
>
> Signed-off-by: Yazen Ghannam <Yazen.Ghannam@xxxxxxx>
> Cc: <stable@xxxxxxxxxxxxxxx> # v4.4..
> Fixes: 3849e91f571d ("x86/AMD: Fix last level cache topology for AMD Fam17h systems")
> ---
I'll run it soon.
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
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