On Tue, 2016-09-20 at 09:07 -0700, Loc Ho wrote:
> Hi,
>
> >> 4.4-stable review patch. If anyone has any objections, please let me know.
> >>
> >> ------------------
> >>
> >> [ Upstream commit 1382ea631ddddb634850a3795527db0feeff5aaf ]
> >>
> >> The X-Gene clock driver missed the divider shift operation when
> >> set the divider value.
> >>
> >> Signed-off-by: Loc Ho <lho@xxxxxxx>
> >> Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver")
> >> Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
> >> Signed-off-by: Sasha Levin <alexander.levin@xxxxxxxxxxx>
> >> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
> >> ---
> >> drivers/clk/clk-xgene.c | 3 ++-
> >> 1 file changed, 2 insertions(+), 1 deletion(-)
> >>
> >> --- a/drivers/clk/clk-xgene.c
> >> +++ b/drivers/clk/clk-xgene.c
> >> @@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk
> >> /* Set new divider */
> >> data = xgene_clk_read(pclk->param.divider_reg +
> >> pclk->param.reg_divider_offset);
> >> - data &= ~((1 << pclk->param.reg_divider_width) - 1);
> >> + data &= ~((1 << pclk->param.reg_divider_width) - 1)
> >> + << pclk->param.reg_divider_shift;
> > [...]
> >
> > This still does the wrong thing when the shift value is non-zero: it
> > clears all bits to the right of the divider field in data. I think the
> > correct assignment is:
> >
> > data &= ~(((1 << pclk->param.reg_divider_width) - 1)
> > << pclk->param.reg_divider_shift);
> >
>
> Yes... There was an later patch that address this -
> https://patchwork.kernel.org/patch/8458361
But it didn't go into this stable update, because you didn't point that
out during review.
Greg, the upstream commit is:
commit 0f4c7a138dfefb0ebdbaf56e3ba2acd2958a6605
Author: Loc Ho <lho@xxxxxxx>
Date: Mon Feb 29 14:15:43 2016 -0700
clk: xgene: Add missing parenthesis when clearing divider value
Ben.
--
Ben Hutchings
Software Developer, Codethink Ltd.
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