Re: [PATCH] drm/i915: Account for TSEG size when determining 865G stolen base

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On Mon, Aug 08, 2016 at 01:58:39PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> 
> Looks like the TSEG lives just above TOUD, stolen comes after TSEG.
> 
> The spec seems somewhat self-contradictory in places, in the ESMRAMC
> register desctription it says:
>  TSEG Size:
>   10=(TOUD + 512 KB) to TOUD
>   11 =(TOUD + 1 MB) to TOUD
> 
> so that agrees with TSEG being at TOUD. But the example given
> elsehwere in the spec says:
> 
>  TOUD equals 62.5 MB = 03E7FFFFh
>  TSEG selected as 512 KB in size,
>  Graphics local memory selected as 1 MB in size
>  General System RAM available in system = 62.5 MB
>  General system RAM range00000000h to 03E7FFFFh
>  TSEG address range03F80000h to 03FFFFFFh
>  TSEG pre-allocated from03F80000h to 03FFFFFFh
>  Graphics local memory pre-allocated from03E80000h to 03F7FFFFh

Found that example:

"""
Notes on Pre-Allocated Memory for Graphics

These register bits control the use of memory from main memory space as
graphics local memory.  The memory for TSEG is pre-allocated first and
then the graphics local memory is pre-allocated. 
"""
 
> so here we have TSEG above stolen.
> 
> Real world evidence agrees with the TOUD->TSEG->stolen order however, so
> let's fix up the code to account for the TSEG size.
> 
> Cc: Taketo Kabe <fdporg@xxxxxxxxxxx>
> Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Daniel Vetter <daniel.vetter@xxxxxxxx>
> Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
> Cc: Ingo Molnar <mingo@xxxxxxxxxx>
> Cc: "H. Peter Anvin" <hpa@xxxxxxxxx>
> Cc: x86@xxxxxxxxxx
> Cc: stable@xxxxxxxxxxxxxxx
> Fixes: 0ad98c74e093 ("drm/i915: Determine the stolen memory base address on gen2")
> Fixes: a4dff76924fe ("x86/gpu: Add Intel graphics stolen memory quirk for gen2 platforms")
> Reported-by: Taketo Kabe <fdporg@xxxxxxxxxxx>
> Tested-by: Taketo Kabe <fdporg@xxxxxxxxxxx>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96473
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>

Link: http://download.intel.com/design/chipsets/datashts/25251405.pdf
Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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