On Wed, Jul 6, 2016 at 11:50 AM, Andy Shevchenko
<andriy.shevchenko@xxxxxxxxxxxxxxx> wrote:
> The commit d56d6b3d7d69 ("gpio: langwell: add Intel Merrifield support")
> doesn't look at all as a proper support for Intel Merrifield and I dare to say
> that it distorts the behaviour of the hardware.
>
> The register map is different on Intel Merrifield, i.e. only 6 out of 8
> register have the same purpose but none of them has same location in the
> address space. The current case potentially harmful to existing hardware since
> it's poking registers on wrong offsets and may set some pin to be GPIO output
> when connected hardware doesn't expect such.
>
> Besides the above GPIO and pinctrl on Intel Merrifield have been located in
> different IP blocks. The functionality has been extended as well, i.e. added
> support of level interrupts, special registers for wake capable sources and
> thus, in my opinion, requires a completele separate driver.
>
> If someone wondering the existing gpio-intel-mid.c would be converted to actual
> pinctrl (which by the fact it is now), though I wouldn't be a volunteer to do
> that.
>
> Fixes: d56d6b3d7d69 ("gpio: langwell: add Intel Merrifield support")
> Cc: stable@xxxxxxxxxxxxxxx # v3.13+
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
Patch applied with Mika's review tag.
Yours,
Linus Walleij
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