This is a note to let you know that I've just added the patch titled
drm/i915: Fix watermarks for VLV/CHV
to the 4.5-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-i915-fix-watermarks-for-vlv-chv.patch
and it can be found in the queue-4.5 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From caed361d83b204b7766924b80463bf7502ee7986 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@xxxxxxxxxxxxxxx>
Date: Wed, 9 Mar 2016 19:07:25 +0200
Subject: drm/i915: Fix watermarks for VLV/CHV
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From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
commit caed361d83b204b7766924b80463bf7502ee7986 upstream.
commit 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.")
broke thigns by removing the pre vs. post wm update distinction. We also
lost the pre plane wm update entirely for VLV/CHV from the crtc enable
path.
This caused underruns on modeset and plane enable/disable on CHV,
and often those can lead to a dead pipe.
So let's bring back the pre vs. post thing, and let's toss in an
explicit wm update to valleyview_crtc_enable() to avoid having to
put it into the common code.
This is more or less a partial revert of the offending commit.
Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
Cc: drm-intel-fixes@xxxxxxxxxxxxxxxxxxxxx
Fixes: 92826fcdfc14 ("drm/i915: Calculate watermark related members in the crtc_state, v4.")
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Link: http://patchwork.freedesktop.org/patch/msgid/1457543247-13987-4-git-send-email-ville.syrjala@xxxxxxxxxxxxxxx
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_atomic.c | 3 ++-
drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++++------
drivers/gpu/drm/i915/intel_drv.h | 2 +-
3 files changed, 18 insertions(+), 8 deletions(-)
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -96,7 +96,8 @@ intel_crtc_duplicate_state(struct drm_cr
crtc_state->update_pipe = false;
crtc_state->disable_lp_wm = false;
crtc_state->disable_cxsr = false;
- crtc_state->wm_changed = false;
+ crtc_state->update_wm_pre = false;
+ crtc_state->update_wm_post = false;
return &crtc_state->base;
}
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4816,7 +4816,7 @@ static void intel_post_plane_update(stru
crtc->wm.cxsr_allowed = true;
- if (pipe_config->wm_changed && pipe_config->base.active)
+ if (pipe_config->update_wm_post && pipe_config->base.active)
intel_update_watermarks(&crtc->base);
if (atomic->update_fbc)
@@ -4850,7 +4850,7 @@ static void intel_pre_plane_update(struc
intel_set_memory_cxsr(dev_priv, false);
}
- if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
+ if (!needs_modeset(&pipe_config->base) && pipe_config->update_wm_pre)
intel_update_watermarks(&crtc->base);
}
@@ -6229,6 +6229,7 @@ static void valleyview_crtc_enable(struc
intel_crtc_load_lut(crtc);
+ intel_update_watermarks(crtc);
intel_enable_pipe(intel_crtc);
assert_vblank_disabled(crtc);
@@ -11881,8 +11882,14 @@ int intel_plane_atomic_calc_changes(stru
plane->base.id, was_visible, visible,
turn_off, turn_on, mode_changed);
- if (turn_on || turn_off) {
- pipe_config->wm_changed = true;
+ if (turn_on) {
+ pipe_config->update_wm_pre = true;
+
+ /* must disable cxsr around plane enable/disable */
+ if (plane->type != DRM_PLANE_TYPE_CURSOR)
+ pipe_config->disable_cxsr = true;
+ } else if (turn_off) {
+ pipe_config->update_wm_post = true;
/* must disable cxsr around plane enable/disable */
if (plane->type != DRM_PLANE_TYPE_CURSOR) {
@@ -11891,7 +11898,9 @@ int intel_plane_atomic_calc_changes(stru
pipe_config->disable_cxsr = true;
}
} else if (intel_wm_need_update(plane, plane_state)) {
- pipe_config->wm_changed = true;
+ /* FIXME bollocks */
+ pipe_config->update_wm_pre = true;
+ pipe_config->update_wm_post = true;
}
if (visible || was_visible)
@@ -12036,7 +12045,7 @@ static int intel_crtc_atomic_check(struc
}
if (mode_changed && !crtc_state->active)
- pipe_config->wm_changed = true;
+ pipe_config->update_wm_post = true;
if (mode_changed && crtc_state->enable &&
dev_priv->display.crtc_compute_clock &&
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -367,7 +367,7 @@ struct intel_crtc_state {
bool update_pipe; /* can a fast modeset be performed? */
bool disable_cxsr;
- bool wm_changed; /* watermarks are updated */
+ bool update_wm_pre, update_wm_post; /* watermarks are updated */
/* Pipe source size (ie. panel fitter input size)
* All planes will be positioned inside this space,
Patches currently in stable-queue which might be from ville.syrjala@xxxxxxxxxxxxxxx are
queue-4.5/drm-i915-fix-watermarks-for-vlv-chv.patch
queue-4.5/drm-i915-psr-try-to-program-link-training-times-correctly.patch
queue-4.5/mfd-intel_soc_pmic_core-terminate-panel-control-gpio-lookup-table-correctly.patch
queue-4.5/drm-i915-don-t-leave-old-junk-in-ilk-active-watermarks-on-readout.patch
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