This is a note to let you know that I've just added the patch titled
clk: qcom: msm8960: fix ce3_core clk enable register
to the 4.5-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
clk-qcom-msm8960-fix-ce3_core-clk-enable-register.patch
and it can be found in the queue-4.5 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 732d6913691848db9fabaa6a25b4d6fad10ddccf Mon Sep 17 00:00:00 2001
From: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
Date: Mon, 22 Feb 2016 11:43:39 +0000
Subject: clk: qcom: msm8960: fix ce3_core clk enable register
From: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
commit 732d6913691848db9fabaa6a25b4d6fad10ddccf upstream.
This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/clk/qcom/gcc-msm8960.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -2769,7 +2769,7 @@ static struct clk_branch ce3_core_clk =
.halt_reg = 0x2fdc,
.halt_bit = 5,
.clkr = {
- .enable_reg = 0x36c4,
+ .enable_reg = 0x36cc,
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "ce3_core_clk",
Patches currently in stable-queue which might be from srinivas.kandagatla@xxxxxxxxxx are
queue-4.5/clk-qcom-msm8960-fix-ce3_src-register-offset.patch
queue-4.5/clk-qcom-msm8960-fix-ce3_core-clk-enable-register.patch
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