As we initialize our own gamma LUT to sane values during initialisation,
we should also update the user visible gamma ramp to match our settings.
And before touching the storage for the user visible gamma ramp, we also
need to check for an allocation failure.
Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
---
drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5988bda..041e07a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8983,11 +8983,18 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
- drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
+ if (!drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256)) {
+ drm_crtc_cleanup(&intel_crtc->base);
+ kfree(intel_crtc);
+ return;
+ }
for (i = 0; i < 256; i++) {
intel_crtc->lut_r[i] = i;
intel_crtc->lut_g[i] = i;
intel_crtc->lut_b[i] = i;
+ intel_crtc->base.gamma_store[i + 0*256] = i << 8;
+ intel_crtc->base.gamma_store[i + 1*256] = i << 8;
+ intel_crtc->base.gamma_store[i + 2*256] = i << 8;
}
/* Swap pipes & planes for FBC on pre-965 */
--
1.8.3.1
--
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