On Tue, Apr 12, 2016 at 04:58:07PM +0300, Mika Kuoppala wrote: > Michał Winiarski <michal.winiarski@xxxxxxxxx> writes: > > > [ text/plain ] > > We started to use PIPE_CONTROL to write render ring seqno in order to > > combat seqno write vs interrupt generation problems. This was introduced > > by commit 7c17d377374d ("drm/i915: Use ordered seqno write interrupt > > generation on gen8+ execlists"). > > > > On gen8+ size of PIPE_CONTROL with Post Sync Operation should be > > 6 dwords. When we're using older 5-dword variant it's possible to > > observe inconsistent values written by PIPE_CONTROL with Post > > Sync Operation from user batches, resulting in rendering corruptions. > > > > v2: Fix BAT failures > > v3: Comments on alignment and thrashing high dword of seqno (Chris) > > v4: Updated commit msg (Mika) > > > > Testcase: igt/gem_pipe_control_store_loop/*-qword-write > > Issue: VIZ-7393 > > Cc: stable@xxxxxxxxxxxxxxx > > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > > Cc: Abdiel Janulgue <abdiel.janulgue@xxxxxxxxxxxxxxx> > > Signed-off-by: Michał Winiarski <michal.winiarski@xxxxxxxxx> > > Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris -- Chris Wilson, Intel Open Source Technology Centre -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html