According to E-EDID spec 1.3, table 3.9, a digital video sink with the
"DFP 1.x compliant TMDS" bit set is "signal compatible with VESA DFP 1.x
TMDS CRGB, 1 pixel / clock, up to 8 bits / color MSB aligned".
For such displays, the DFP spec 1.0, section 3.10 "EDID support" says:
"If the DFP monitor only supports EDID 1.X (1.1, 1.2, etc.)
without extensions, the host will make the following assumptions:
1. 24-bit MSB-aligned RGB TFT
2. DE polarity is active high
3. H and V syncs are active high
4. Established CRT timings will be used
5. Dithering will not be enabled on the host"
So if we don't know the bit depth of the display from additional
colorimetry info we should assume 8 bpc / 24 bpp with no dithering
by default.
This patch adds info->bpc = 8 assignement for that case.
Now the DVI 1.0 spec (section 2.2.11.2 "Monitor data format support")
mandates that "...If the monitor implements the EDID 2.0, 1.3 or newer
data structure the monitor may specify any data format that is definable
within the EDID data structure used. In all cases the monitor must support
the 24-bit MSB aligned RGB TFT data format as a minimum."
So any DVI display with EDID 1.3 should also have at least info->bpc = 8,
even if the "DFP 1.x compliant" bit isn't set, but in our EDID handling
we don't know if the EDID comes from a DVI display or something else. I
therefore don't know if it is safe to always assume 8 bpc for digital
inputs?
Most of my tested DVI sinks set the DFP bit, but one tested Dell panel
doesn't.
Lack of handling this correctly was exposed by commit 013dd9e03872
("drm/i915/dp: fall back to 18 bpp when sink capability is unknown")
which assumes that the sink capability is unknown if our edid handling
reports 0 bpc.
As we return bpc = 0 for such displays, that patch will cause a
degradation of output precison to 6 bpc for such displays on Intel hw
if they are connected via an active DP->dual-link DVI converter and
thereby treated as Displayport.
As that patch was backported to stable we should include this one
also in stable to fix the regression in color depth for such panels.
Signed-off-by: Mario Kleiner <mario.kleiner.de@xxxxxxxxx>
Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
---
drivers/gpu/drm/drm_edid.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 414d7f6..ff28815 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3810,8 +3810,12 @@ static void drm_add_display_info(struct edid *edid,
if (edid->revision < 3)
return;
- if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
+ if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) {
+ /* Analog sinks = infinite bpc, but driver decides */
+ DRM_DEBUG("%s: Assigning analog sink color depth as %d bpc.\n",
+ connector->name, info->bpc);
return;
+ }
/* Get data from CEA blocks if present */
edid_ext = drm_find_cea_extension(edid);
@@ -3829,6 +3833,31 @@ static void drm_add_display_info(struct edid *edid,
/* HDMI deep color modes supported? Assign to info, if so */
drm_assign_hdmi_deep_color_info(edid, info, connector);
+ /*
+ * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
+ *
+ * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
+ * says:
+ *
+ * "If the DFP monitor only supports EDID 1.X (1.1, 1.2, etc.)
+ * without extensions, the host will make the following assumptions:
+ *
+ * 1. 24-bit MSB-aligned RGB TFT
+ * 2. DE polarity is active high
+ * 3. H and V syncs are active high
+ * 4. Established CRT timings will be used
+ * 5. Dithering will not be enabled on the host"
+ *
+ * So we use 8 bpc in this case and "no dithering" will hopefully
+ * follow.
+ */
+ if ((info->bpc == 0) && (edid->revision < 4) &&
+ (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
+ info->bpc = 8;
+ DRM_DEBUG("%s: Assigning DFP/DVI sink color depth as %d bpc.\n",
+ connector->name, info->bpc);
+ }
+
/* Only defined for 1.4 with digital displays */
if (edid->revision < 4)
return;
--
2.7.0
--
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