On Wed, Mar 16, 2016 at 02:03:35PM +0000, Mark Rutland wrote: > If I understand correctly, the main reason that we need this for correctness is > non-coherent DMA to/from SLAB caches. > > A more general approach (and more invasive, but perhaps less so than making > ARCH_DMA_MINALIGN usage completely dynamic) would be to determine at runtime > whether the CWG is larger than the configured ARCH_DMA_MINALIGN, and if so, > force the use of bounce buffers (which could be padded to the architectural > maximum of 2K) for non-coherent DMA. That nicely degrades to not mattering for > the case of coherent DMA. > > I would consider NoSnoop a separate case. It's closer to "negatively coherent", > and always required page-aligned buffer anyway due to MMU behaviour. What makes you say that? There are no such alignment requirements for buffers that may be accessed with a NoSnoop transaction. On ARM, we'll have a mismatched alias, but we'd need to solve that with explicit cache maintenance (and my understanding is that's what things like GPU drivers already do on x86). Will -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html