On Wed, Oct 21, 2015 at 12:36:38PM -0700, Paul E. McKenney wrote: > On Wed, Oct 21, 2015 at 10:18:33AM +0200, Peter Zijlstra wrote: > > On Tue, Oct 20, 2015 at 02:28:35PM -0700, Paul E. McKenney wrote: > > > I am not seeing a sync there, but I really have to defer to the > > > maintainers on this one. I could easily have missed one. > > > > So x86 implies a full barrier for everything that changes the CPL; and > > some form of implied ordering seems a must if you change the privilege > > level unless you tag every single load/store with the priv level at that > > time, which seems the more expensive option. > > And it is entirely possible that there is some similar operation > somewhere in the powerpc entry/exit code. I would not trust myself > to recognize it, though. > > > So I suspect the typical implementation will flush all load/stores, > > change the effective priv level and continue. > > > > This can of course be implemented at a pure per CPU ordering (RCpc), > > which would be in line with the rest of Power, in which case you do > > indeed need an explicit sync to make it visible to other CPUs. > > > > But yes, if Michael or Ben could clarify this it would be good. > > Michael and Ben, ping for this, thank you ;-) Regards, Boqun > > Back then I talked to Ralf about what MIPS says on this, and MIPS arch > > spec is entirely quiet on this, it allows implementations full freedom > > IIRC. > > :-) ;-) ;-) > > > </ramble> > > Thanx, Paul >
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