This is a note to let you know that I've just added the patch titled
drm/amdgpu: fix typo in dce11 watermark setup
to the 4.2-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch
and it can be found in the queue-4.2 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 99a092383794e07d60644b449a01656da112eb1f Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@xxxxxxx>
Date: Thu, 3 Sep 2015 10:16:23 -0400
Subject: drm/amdgpu: fix typo in dce11 watermark setup
From: Alex Deucher <alexander.deucher@xxxxxxx>
commit 99a092383794e07d60644b449a01656da112eb1f upstream.
Using the wrong watermwark value for the secondary
watermark. Copy paste typo. Noticed by Mykola.
Reviewed-by: Harry Wentland <harry.wentland@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1329,7 +1329,7 @@ static void dce_v11_0_program_watermarks
tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
- tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
+ tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
/* restore original selection */
Patches currently in stable-queue which might be from alexander.deucher@xxxxxxx are
queue-4.2/drm-amdgpu-atom-send-out-the-full-aux-address.patch
queue-4.2/drm-radeon-atom-send-out-the-full-aux-address.patch
queue-4.2/drm-amdgpu-fix-ih-ring-allocation-for-bus-addresses-v2.patch
queue-4.2/drm-radeon-don-t-link-train-displayport-on-hpd-until-we-get-the-dpcd.patch
queue-4.2/drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch
queue-4.2/drm-radeon-native-send-out-the-full-aux-address.patch
queue-4.2/drm-amdgpu-don-t-link-train-displayport-on-hpd-until-we-get-the-dpcd.patch
queue-4.2/drm-radeon-fix-hdmi-quantization_range-for-pre-dce5-asics.patch
queue-4.2/drm-amdgpu-fix-typo-in-dce10-watermark-setup.patch
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