Patch "drm/radeon: properly lock disp in mc_stop/resume for r5xx-r7xx" has been added to the 3.8-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/radeon: properly lock disp in mc_stop/resume for r5xx-r7xx

to the 3.8-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-radeon-properly-lock-disp-in-mc_stop-resume-for-r5xx-r7xx.patch
and it can be found in the queue-3.8 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.


>From 2f86e2ede39a98650c2d465857405ef1c51372b1 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@xxxxxxx>
Date: Wed, 10 Apr 2013 09:47:05 -0400
Subject: drm/radeon: properly lock disp in mc_stop/resume for r5xx-r7xx

From: Alex Deucher <alexander.deucher@xxxxxxx>

commit 2f86e2ede39a98650c2d465857405ef1c51372b1 upstream.

Need to wait for the new addresses to take affect before
re-enabling the MC.

Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>

---
 drivers/gpu/drm/radeon/r500_reg.h |    1 
 drivers/gpu/drm/radeon/rv515.c    |   43 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -357,6 +357,7 @@
 #define AVIVO_D1CRTC_FRAME_COUNT                                0x60a4
 #define AVIVO_D1CRTC_STEREO_CONTROL                             0x60c4
 
+#define AVIVO_D1MODE_MASTER_UPDATE_LOCK                         0x60e0
 #define AVIVO_D1MODE_MASTER_UPDATE_MODE                         0x60e4
 
 /* master controls */
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -338,6 +338,22 @@ void rv515_mc_stop(struct radeon_device
 	}
 	/* wait for the MC to settle */
 	udelay(100);
+
+	/* lock double buffered regs */
+	for (i = 0; i < rdev->num_crtc; i++) {
+		if (save->crtc_enabled[i]) {
+			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
+			if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
+				tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
+				WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
+			}
+			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
+			if (!(tmp & 1)) {
+				tmp |= 1;
+				WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
+			}
+		}
+	}
 }
 
 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
@@ -367,6 +383,33 @@ void rv515_mc_resume(struct radeon_devic
 	}
 	WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
 
+	/* unlock regs and wait for update */
+	for (i = 0; i < rdev->num_crtc; i++) {
+		if (save->crtc_enabled[i]) {
+			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
+			if ((tmp & 0x3) != 0) {
+				tmp &= ~0x3;
+				WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
+			}
+			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
+			if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
+				tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
+				WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
+			}
+			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
+			if (tmp & 1) {
+				tmp &= ~1;
+				WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
+			}
+			for (j = 0; j < rdev->usec_timeout; j++) {
+				tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
+				if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
+					break;
+				udelay(1);
+			}
+		}
+	}
+
 	if (rdev->family >= CHIP_R600) {
 		/* unblackout the MC */
 		if (rdev->family >= CHIP_RV770)


Patches currently in stable-queue which might be from alexander.deucher@xxxxxxx are

queue-3.8/drm-radeon-fix-typo-in-rv515_mc_resume.patch
queue-3.8/drm-radeon-update-wait_for_vblank-for-evergreen.patch
queue-3.8/drm-radeon-add-some-new-si-pci-ids.patch
queue-3.8/drm-radeon-dce6-add-missing-display-reg-for-tiling-setup.patch
queue-3.8/drm-radeon-don-t-use-get_engine_clock-on-apus.patch
queue-3.8/drm-radeon-update-wait_for_vblank-for-r5xx-r7xx.patch
queue-3.8/drm-radeon-properly-lock-disp-in-mc_stop-resume-for-r5xx-r7xx.patch
queue-3.8/drm-radeon-update-wait_for_vblank-for-r1xx-r4xx.patch
queue-3.8/drm-radeon-disable-the-crtcs-in-mc_stop-evergreen-v2.patch
queue-3.8/drm-radeon-use-frac-fb-div-on-rs780-rs880.patch
queue-3.8/drm-radeon-properly-lock-disp-in-mc_stop-resume-for-evergreen.patch
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