On Mon, Apr 22, 2013 at 09:40:06AM -0700, gregkh@xxxxxxxxxxxxxxxxxxx wrote: > > This is a note to let you know that I've just added the patch titled > > perf/x86: Fix offcore_rsp valid mask for SNB/IVB > > to the 3.4-stable tree which can be found at: > http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary > > The filename of the patch is: > perf-x86-fix-offcore_rsp-valid-mask-for-snb-ivb.patch > and it can be found in the queue-3.4 subdirectory. > > If you, or anyone else, feels it should not be added to the stable tree, > please let <stable@xxxxxxxxxxxxxxx> know about it. > > > From f1923820c447e986a9da0fc6bf60c1dccdf0408e Mon Sep 17 00:00:00 2001 > From: Stephane Eranian <eranian@xxxxxxxxxx> > Date: Tue, 16 Apr 2013 13:51:43 +0200 > Subject: perf/x86: Fix offcore_rsp valid mask for SNB/IVB > > From: Stephane Eranian <eranian@xxxxxxxxxx> > > commit f1923820c447e986a9da0fc6bf60c1dccdf0408e upstream. > > The valid mask for both offcore_response_0 and > offcore_response_1 was wrong for SNB/SNB-EP, > IVB/IVB-EP. It was possible to write to > reserved bit and cause a GP fault crashing > the kernel. > > This patch fixes the problem by correctly marking the > reserved bits in the valid mask for all the processors > mentioned above. > > A distinction between desktop and server parts is introduced > because bits 24-30 are only available on the server parts. > > This version of the patch is just a rebase to perf/urgent tree > and should apply to older kernels as well. > > Signed-off-by: Stephane Eranian <eranian@xxxxxxxxxx> > Cc: peterz@xxxxxxxxxxxxx > Cc: jolsa@xxxxxxxxxx > Cc: ak@xxxxxxxxxxxxxxx > Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx> > Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> > > --- > arch/x86/kernel/cpu/perf_event_intel.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > > --- a/arch/x86/kernel/cpu/perf_event_intel.c > +++ b/arch/x86/kernel/cpu/perf_event_intel.c > @@ -126,8 +126,14 @@ static struct event_constraint intel_gen > }; > > static struct extra_reg intel_snb_extra_regs[] __read_mostly = { > - INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), > - INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), > + INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), > + INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), > + EVENT_EXTRA_END > +}; > + > +static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { > + INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), > + INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), > EVENT_EXTRA_END > }; > > @@ -1852,6 +1858,10 @@ __init int intel_pmu_init(void) > x86_pmu.event_constraints = intel_snb_event_constraints; > x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; > x86_pmu.extra_regs = intel_snb_extra_regs; Please consider removing the line above ^^^^^ Looking at the original commit, the line above should have been removed by this patch. Since the code immediately after this line actually changes the value of x86_pmu.extra_regs again, it really shouldn't make any difference anyway (and the compiler will probably optimise out the line). Cheers, -- Luis > + if (boot_cpu_data.x86_model == 45) > + x86_pmu.extra_regs = intel_snbep_extra_regs; > + else > + x86_pmu.extra_regs = intel_snb_extra_regs; > /* all extra regs are per-cpu when HT is on */ > x86_pmu.er_flags |= ERF_HAS_RSP_1; > x86_pmu.er_flags |= ERF_NO_HT_SHARING; > > > Patches currently in stable-queue which might be from eranian@xxxxxxxxxx are > > queue-3.4/perf-x86-fix-offcore_rsp-valid-mask-for-snb-ivb.patch > -- > To unsubscribe from this list: send the line "unsubscribe stable" in > the body of a message to majordomo@xxxxxxxxxxxxxxx > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html