Hello Greg, Am Mon, Feb 24, 2025 at 03:19:04PM +0100 schrieb gregkh@xxxxxxxxxxxxxxxxxxx: > > This is a note to let you know that I've just added the patch titled > > spi: atmel-quadspi: Avoid overwriting delay register settings > > to the 6.1-stable tree which can be found at: > http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary > > The filename of the patch is: > spi-atmel-quadspi-avoid-overwriting-delay-register-settings.patch > and it can be found in the queue-6.1 subdirectory. > > If you, or anyone else, feels it should not be added to the stable tree, > please let <stable@xxxxxxxxxxxxxxx> know about it. > > > From 329ca3eed4a9a161515a8714be6ba182321385c7 Mon Sep 17 00:00:00 2001 > From: Alexander Dahl <ada@xxxxxxxxxxx> > Date: Wed, 18 Sep 2024 10:27:43 +0200 > Subject: spi: atmel-quadspi: Avoid overwriting delay register settings > > From: Alexander Dahl <ada@xxxxxxxxxxx> > > commit 329ca3eed4a9a161515a8714be6ba182321385c7 upstream. > > Previously the MR and SCR registers were just set with the supposedly > required values, from cached register values (cached reg content > initialized to zero). > > All parts fixed here did not consider the current register (cache) > content, which would make future support of cs_setup, cs_hold, and > cs_inactive impossible. > > Setting SCBR in atmel_qspi_setup() erases a possible DLYBS setting from > atmel_qspi_set_cs_timing(). The DLYBS setting is applied by ORing over > the current setting, without resetting the bits first. All writes to MR > did not consider possible settings of DLYCS and DLYBCT. > > Signed-off-by: Alexander Dahl <ada@xxxxxxxxxxx> > Fixes: f732646d0ccd ("spi: atmel-quadspi: Add support for configuring CS timing") > Link: https://patch.msgid.link/20240918082744.379610-2-ada@xxxxxxxxxxx > Signed-off-by: Mark Brown <broonie@xxxxxxxxxx> > Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> > --- > drivers/spi/atmel-quadspi.c | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > --- a/drivers/spi/atmel-quadspi.c > +++ b/drivers/spi/atmel-quadspi.c > @@ -388,9 +388,9 @@ static int atmel_qspi_set_cfg(struct atm > * If the QSPI controller is set in regular SPI mode, set it in > * Serial Memory Mode (SMM). > */ > - if (aq->mr != QSPI_MR_SMM) { > - atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); > - aq->mr = QSPI_MR_SMM; > + if (!(aq->mr & QSPI_MR_SMM)) { > + aq->mr |= QSPI_MR_SMM; > + atmel_qspi_write(aq->scr, aq, QSPI_MR); This has a bug fixed later with commit 162d9b5d2308c7e48efbc97d36babbf4d73b2c61 ("spi: atmel-quadspi: Fix wrong register value written to MR"). You should also pick that one. Thanks and Greets Alex > } > > /* Clear pending interrupts */ > @@ -545,7 +545,8 @@ static int atmel_qspi_setup(struct spi_d > if (ret < 0) > return ret; > > - aq->scr = QSPI_SCR_SCBR(scbr); > + aq->scr &= ~QSPI_SCR_SCBR_MASK; > + aq->scr |= QSPI_SCR_SCBR(scbr); > atmel_qspi_write(aq->scr, aq, QSPI_SCR); > > pm_runtime_mark_last_busy(ctrl->dev.parent); > @@ -578,6 +579,7 @@ static int atmel_qspi_set_cs_timing(stru > if (ret < 0) > return ret; > > + aq->scr &= ~QSPI_SCR_DLYBS_MASK; > aq->scr |= QSPI_SCR_DLYBS(cs_setup); > atmel_qspi_write(aq->scr, aq, QSPI_SCR); > > @@ -593,8 +595,8 @@ static void atmel_qspi_init(struct atmel > atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR); > > /* Set the QSPI controller by default in Serial Memory Mode */ > - atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); > - aq->mr = QSPI_MR_SMM; > + aq->mr |= QSPI_MR_SMM; > + atmel_qspi_write(aq->mr, aq, QSPI_MR); > > /* Enable the QSPI controller */ > atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); > > > Patches currently in stable-queue which might be from ada@xxxxxxxxxxx are > > queue-6.1/spi-atmel-quadspi-avoid-overwriting-delay-register-settings.patch
